Core hang via invalid CSR shadow write
Published Apr 20, 2026 · Updated Apr 20, 2026
Improper exception handling in XiangShan allows local users to hang a processor core through crafted CSR operations. NewCSR performs shadow writes to custom PMA CSRs absent from csrRwMap; the resulting illegal-instruction exception fails to enter mtvec. Execution in machine mode on the affected core is required, and the demonstrated consequence is disrupted control flow and core unavailability rather than data disclosure.
Summary
What happened
Improper exception handling in XiangShan allows local users to hang a processor core through crafted CSR operations. NewCSR performs shadow writes to custom PMA CSRs absent from csrRwMap; the resulting illegal-instruction exception fails to enter mtvec. Execution in machine mode on the affected core is required, and the demonstrated consequence is disrupted control flow and core unavailability rather than data disclosure.
The record
- CVE
- CVE-2026-29643
- Published
- Apr 20, 2026
- Updated
- Apr 20, 2026
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-703, T1499.004
- Attack vector
- local
- Privileges
- Unavailable
Timeline
How it unfolded
- Apr 20, 2026CVE publishedPublication date reported by the CVE source.
- Apr 20, 2026Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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What is affected?
Affected products and versions are unavailable in this record.
Published CVSS scores
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Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
- ill-test.zip XiangShan illegal-instruction reproducerproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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