Secret disclosure via L1 write-port contention
Published Aug 9, 2025 · Updated Aug 12, 2025
Observable timing discrepancy in SonicBOOM 2.2.0 through 2.2.3 allows local users to infer secret data through L1 cache timing. The single BoomDataArray_array write port gives LSU stores priority over MSHR refills, so a transient secret-dependent store storm delays cache-miss recovery. Exploitation requires low-privileged local code, branch mistraining, a forced cache miss, and repeated cycle measurements; experiments reported 15 Kb/s leakage.
Summary
What happened
Observable timing discrepancy in SonicBOOM 2.2.0 through 2.2.3 allows local users to infer secret data through L1 cache timing. The single BoomDataArray_array write port gives LSU stores priority over MSHR refills, so a transient secret-dependent store storm delays cache-miss recovery. Exploitation requires low-privileged local code, branch mistraining, a forced cache miss, and repeated cycle measurements; experiments reported 15 Kb/s leakage.
The record
- CVE
- CVE-2025-8774
- Published
- Aug 9, 2025
- Updated
- Aug 12, 2025
- Vendor
- RISCV-BOOM
- Product
- SonicBOOM
- Classifications
- CWE-208, CWE-203
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Aug 9, 2025CVE publishedPublication date reported by the CVE source.
- Aug 12, 2025Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
Compare these published version ranges with your installed build and any vendor patches.
- Affected versionversion=2.2.0
- Affected versionversion=2.2.1
- Affected versionversion=2.2.2
- Affected versionversion=2.2.3
What conditions does exploitation require?
What is affected?
Published CVSS scores
CVSS describes severity. EPSS estimates exploitation probability.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Public exploit references
- MSHRush proof of conceptproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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