System crash via zero PMU counter mask
Published Jul 27, 2026 · Updated Jul 27, 2026
Input validation failure in OpenSBI 1.3 through 1.6 allows local users controlling S-mode software to crash the system via a PMU call. The sbi_pmu_ctr_cfg_match path accepts a zero counter_idx_mask, derives counter index 63, reads active_events out of bounds, and writes nonexistent CSR 0xb3f. Control of privileged S-mode or HS-mode software is required, and the resulting M-mode firmware crash interrupts the entire system without reported data disclosure or modification.
Summary
What happened
Input validation failure in OpenSBI 1.3 through 1.6 allows local users controlling S-mode software to crash the system via a PMU call. The sbi_pmu_ctr_cfg_match path accepts a zero counter_idx_mask, derives counter index 63, reads active_events out of bounds, and writes nonexistent CSR 0xb3f. Control of privileged S-mode or HS-mode software is required, and the resulting M-mode firmware crash interrupts the entire system without reported data disclosure or modification.
The record
- CVE
- CVE-2025-63913
- Published
- Jul 27, 2026
- Updated
- Jul 27, 2026
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-400, T1499
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Jul 27, 2026CVE publishedPublication date reported by the CVE source.
- Jul 27, 2026Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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What is affected?
Affected products and versions are unavailable in this record.
Published CVSS scores
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Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Public exploit references
- OpenSBI PMU zero-mask firmware crash reproducerproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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