Privilege retention via incorrect SRET transition
Published Nov 10, 2025 · Updated Nov 12, 2025
Incorrect privilege assignment in CHIPS Alliance Rocket Chip 1.6 and earlier allows remote authenticated users to retain Machine mode. The SRET implementation fails to apply the privilege transition selected by sstatus.SPP, so execution remains in M-mode rather than returning to S-mode. Attackers require low-privileged access to the affected instruction path; the retained privilege can expose machine-level information without reported integrity or availability impact.
Summary
What happened
Incorrect privilege assignment in CHIPS Alliance Rocket Chip 1.6 and earlier allows remote authenticated users to retain Machine mode. The SRET implementation fails to apply the privilege transition selected by sstatus.SPP, so execution remains in M-mode rather than returning to S-mode. Attackers require low-privileged access to the affected instruction path; the retained privilege can expose machine-level information without reported integrity or availability impact.
The record
- CVE
- CVE-2025-63384
- Published
- Nov 10, 2025
- Updated
- Nov 12, 2025
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-266, T1068
- Attack vector
- network
- Privileges
- authenticated
Timeline
How it unfolded
- Nov 10, 2025CVE publishedPublication date reported by the CVE source.
- Nov 12, 2025Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
What conditions does exploitation require?
What is affected?
Affected products and versions are unavailable in this record.
Published CVSS scores
CVSS describes severity. EPSS estimates exploitation probability.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
- RISC-V Rocket Chip SRET reproductionproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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