Program termination via simultaneous MRET exception handling
Published Sep 30, 2025 · Updated Sep 30, 2025
Unexpected processor behavior in Chipsalliance Rocket-Chip commit f517abb and earlier allows attackers to terminate programs during MRET. In CSR.scala, exception-entry and insn_ret branches can both update mstatus when MRET itself raises an exception because the return branch does not exclude the exception condition. Execution must reach MRET in machine mode outside an exception state; the conflicting updates leave MPIE incorrect and terminate the running program.
Summary
What happened
Unexpected processor behavior in Chipsalliance Rocket-Chip commit f517abb and earlier allows attackers to terminate programs during MRET. In CSR.scala, exception-entry and insn_ret branches can both update mstatus when MRET itself raises an exception because the return branch does not exclude the exception condition. Execution must reach MRET in machine mode outside an exception state; the conflicting updates leave MPIE incorrect and terminate the running program.
The record
- CVE
- CVE-2025-56301
- Published
- Sep 30, 2025
- Updated
- Sep 30, 2025
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-1281, T1499
- Attack vector
- network
- Privileges
- unauthenticated
Timeline
How it unfolded
- Sep 30, 2025CVE publishedPublication date reported by the CVE source.
- Sep 30, 2025Record updatedLatest update available in the CVE record.
Exploitability
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What is affected?
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Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
- Rocket-Chip MRET exception demonstrationproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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