Processor misexecution via RTL-netlist interface mismatch
Published Jul 17, 2026 · Updated Jul 17, 2026
Hardware synthesis flaw in RISC-V PicoRV32 commit 87c89a allows context-dependent attackers to corrupt processor execution. The synthesized netlist fails to preserve RTL behavior: the memory interface miscalculates subsequent addresses, while the PCPI decode stage forwards incomplete or incorrect instructions. A crafted memory-address and PCPI-instruction combination produces unknown output, causing incorrect instruction fetching, unintended data retrieval, or faulty custom-instruction execution.
Summary
What happened
Hardware synthesis flaw in RISC-V PicoRV32 commit 87c89a allows context-dependent attackers to corrupt processor execution. The synthesized netlist fails to preserve RTL behavior: the memory interface miscalculates subsequent addresses, while the PCPI decode stage forwards incomplete or incorrect instructions. A crafted memory-address and PCPI-instruction combination produces unknown output, causing incorrect instruction fetching, unintended data retrieval, or faulty custom-instruction execution.
The record
- CVE
- CVE-2025-51678
- Published
- Jul 17, 2026
- Updated
- Jul 17, 2026
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-704, CWE-119
- Attack vector
- network
- Privileges
- unauthenticated
Timeline
How it unfolded
- Jul 17, 2026CVE publishedPublication date reported by the CVE source.
- Jul 17, 2026Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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What is affected?
Affected products and versions are unavailable in this record.
Published CVSS scores
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Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
- SynFuzz PicoRV32 triggering inputproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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