Processor stall via stale program-counter update
Published Aug 26, 2026 · Updated Aug 27, 2026
Denial of service in openRISC OR1200 commit 83ac6b allows context-dependent attackers to stall the processor via an SPR NPC change. The program-counter logic retains the previous PC instead of updating cpu_adr_o when the next-program-counter value in an SPR changes, so instruction fetching stalls. The disclosure does not identify what access is required to change the SPR, and the documented consequence is a processor stall rather than data access or code execution.
Summary
What happened
Denial of service in openRISC OR1200 commit 83ac6b allows context-dependent attackers to stall the processor via an SPR NPC change. The program-counter logic retains the previous PC instead of updating cpu_adr_o when the next-program-counter value in an SPR changes, so instruction fetching stalls. The disclosure does not identify what access is required to change the SPR, and the documented consequence is a processor stall rather than data access or code execution.
The record
- CVE
- CVE-2025-51675
- Published
- Aug 26, 2026
- Updated
- Aug 27, 2026
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-1202, T1499.004
- Attack vector
- Unavailable
- Privileges
- Unavailable
Timeline
How it unfolded
- Aug 26, 2026CVE publishedPublication date reported by the CVE source.
- Aug 27, 2026Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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What is affected?
Affected products and versions are unavailable in this record.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
- SynFuzz OR1200 B7 triggering vectorproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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