Privilege escalation via overlapping protected memory ranges
Published Aug 12, 2025 · Updated Feb 26, 2026
Privilege escalation in Intel Xeon 6 processors with P-cores and Intel TDX allows privileged local users to breach TDX memory isolation. The processor mishandles overlaps between protected memory ranges, allowing access controls for isolated TDX memory to be bypassed. Exploitation requires local high privileges and a specific runtime condition, and it can expose or alter protected data without interrupting service.
Summary
What happened
Privilege escalation in Intel Xeon 6 processors with P-cores and Intel TDX allows privileged local users to breach TDX memory isolation. The processor mishandles overlaps between protected memory ranges, allowing access controls for isolated TDX memory to be bypassed. Exploitation requires local high privileges and a specific runtime condition, and it can expose or alter protected data without interrupting service.
The record
- CVE
- CVE-2025-22889
- Published
- Aug 12, 2025
- Updated
- Feb 26, 2026
- Vendor
- Topcon Positioning Systems, Inc.
- Product
- Intel Xeon 6 Processors
- Classifications
- CWE-1260, CAPEC-679, CAPEC-456, T1068
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Aug 12, 2025CVE publishedPublication date reported by the CVE source.
- Feb 26, 2026Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=See references
What conditions does exploitation require?
What is affected?
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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