Host information disclosure via HPA translation bypass
Published Dec 10, 2024 · Updated Dec 16, 2024
Improper resource exposure in affected Arm CPU cores allows guest OS users to disclose host information through HPA translation errors. Hardware Page Aggregation can cause Stage-1 or Stage-2 address translation to bypass Stage-2 or GPT protection rather than preserving the intended isolation boundary. Reachability requires HPA to remain enabled on an affected core in a virtualization environment where a modified or compromised guest operates.
Summary
What happened
Improper resource exposure in affected Arm CPU cores allows guest OS users to disclose host information through HPA translation errors. Hardware Page Aggregation can cause Stage-1 or Stage-2 address translation to bypass Stage-2 or GPT protection rather than preserving the intended isolation boundary. Reachability requires HPA to remain enabled on an affected core in a virtualization environment where a modified or compromised guest operates.
The record
- CVE
- CVE-2024-5660
- Published
- Dec 10, 2024
- Updated
- Dec 16, 2024
- Vendor
- Arm
- Product
- Cortex-X925
- Classifications
- CWE-668, T1068
- Attack vector
- network
- Privileges
- unauthenticated
Timeline
How it unfolded
- Dec 10, 2024CVE publishedPublication date reported by the CVE source.
- Dec 16, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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- Affected versionversion=0
What conditions does exploitation require?
What is affected?
Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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