Confidential-guest compromise via forged microcode signatures
Published Feb 3, 2025 · Updated Apr 2, 2025
Improper signature verification in AMD EPYC processors allows local users with administrator privileges to compromise SEV-SNP guests. The CPU ROM loader authenticates each patch's embedded RSA public key with a collision-prone AES-CMAC construction, allowing forged keys and signatures to pass. Exploitation requires host ring 0 outside the guest; forged microcode can subvert guest confidentiality and integrity but does not persist through a power cycle.
Summary
What happened
Improper signature verification in AMD EPYC processors allows local users with administrator privileges to compromise SEV-SNP guests. The CPU ROM loader authenticates each patch's embedded RSA public key with a collision-prone AES-CMAC construction, allowing forged keys and signatures to pass. Exploitation requires host ring 0 outside the guest; forged microcode can subvert guest confidentiality and integrity but does not persist through a power cycle.
The record
- CVE
- CVE-2024-56161
- Published
- Feb 3, 2025
- Updated
- Apr 2, 2025
- Vendor
- Advanced Micro Devices, Inc.
- Product
- AMD EPYC 7003 Processors
- Classifications
- CWE-347, T1601.001
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Feb 3, 2025CVE publishedPublication date reported by the CVE source.
- Apr 2, 2025Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
Affected versions are unavailable in this record. Check the vendor advisory for version and patch details.
What conditions does exploitation require?
What is affected?
Published CVSS scores
CVSS describes severity. EPSS estimates exploitation probability.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
- EntrySign Milan and Genoa RDRAND test payloadproof of concept · demonstrated
Labels summarize the accepted research assessment. They do not indicate a test against your environment.
Technologies
Your stack
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Your stack
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