Guest memory modification via faulty SPP enforcement
Published Nov 13, 2024 · Updated Nov 14, 2024
Protection mechanism failure in Intel Xeon 6 E-core processors allows guest OS users to alter protected guest memory through SPP. When a VMM enables SPP, the processor permits writes to 4 KB guest-physical regions that the hypervisor marked nonwritable. Reachability requires low-privileged guest access, EPT sub-page write permissions enabled, and at least one SPP-enabled page mapped into the guest.
Summary
What happened
Protection mechanism failure in Intel Xeon 6 E-core processors allows guest OS users to alter protected guest memory through SPP. When a VMM enables SPP, the processor permits writes to 4 KB guest-physical regions that the hypervisor marked nonwritable. Reachability requires low-privileged guest access, EPT sub-page write permissions enabled, and at least one SPP-enabled page mapped into the guest.
The record
- CVE
- CVE-2024-38660
- Published
- Nov 13, 2024
- Updated
- Nov 14, 2024
- Vendor
- Topcon Positioning Systems, Inc.
- Product
- Intel Xeon 6 Processors
- Classifications
- CWE-693, T1068
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Nov 13, 2024CVE publishedPublication date reported by the CVE source.
- Nov 14, 2024Record updatedLatest update available in the CVE record.
Exploitability
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- Affected versionversion=See references
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What is affected?
Published CVSS scores
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Attacks
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Weakness, pattern, technique
Public exploit references
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Technologies
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Your stack
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