Cross-context data disclosure via L1D false completion
Published Jul 8, 2025 · Updated Nov 4, 2025
Transient execution in AMD Family 19h processors allows local users to infer L1D cache data across privileged contexts. A linear-address microtag can falsely match an absent L1D entry, forwarding invalid data whose effect on other instruction timing reveals the entry associated with that microtag. Exploitation requires arbitrary local code and repeated victim invocation; exposed data can cross kernel, process, hypervisor, and guest boundaries.
Summary
What happened
Transient execution in AMD Family 19h processors allows local users to infer L1D cache data across privileged contexts. A linear-address microtag can falsely match an absent L1D entry, forwarding invalid data whose effect on other instruction timing reveals the entry associated with that microtag. Exploitation requires arbitrary local code and repeated victim invocation; exposed data can cross kernel, process, hypervisor, and guest boundaries.
The record
- CVE
- CVE-2024-36357
- Published
- Jul 8, 2025
- Updated
- Nov 4, 2025
- Vendor
- Advanced Micro Devices, Inc.
- Product
- AMD Ryzen™ 7000 Series Desktop Processors
- Classifications
- CWE-1421
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Jul 8, 2025CVE publishedPublication date reported by the CVE source.
- Nov 4, 2025Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
Affected versions are unavailable in this record. Check the vendor advisory for version and patch details.
What conditions does exploitation require?
What is affected?
Published CVSS scores
CVSS describes severity. EPSS estimates exploitation probability.
Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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