Local TSC_AUX disclosure via transient execution
Published Jul 8, 2025 · Updated Jul 9, 2025
Transient execution in affected AMD processors allows local users to infer TSC_AUX even when software disables direct reads. Under specific microarchitectural scheduling conditions, speculative instruction timing exposes the disabled TSC_AUX value through a side channel. A low-privileged process must execute locally; AMD states that disclosure of TSC_AUX does not expose sensitive information.
Summary
What happened
Transient execution in affected AMD processors allows local users to infer TSC_AUX even when software disables direct reads. Under specific microarchitectural scheduling conditions, speculative instruction timing exposes the disabled TSC_AUX value through a side channel. A low-privileged process must execute locally; AMD states that disclosure of TSC_AUX does not expose sensitive information.
The record
- CVE
- CVE-2024-36349
- Published
- Jul 8, 2025
- Updated
- Jul 9, 2025
- Vendor
- Advanced Micro Devices, Inc.
- Product
- AMD Ryzen™ 7000 Series Desktop Processors
- Classifications
- CWE-1420
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Jul 8, 2025CVE publishedPublication date reported by the CVE source.
- Jul 9, 2025Record updatedLatest update available in the CVE record.
Exploitability
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- Affected versionversion=all
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What is affected?
Published CVSS scores
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Attacks
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Technologies
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