Local control-register disclosure via speculative execution
Published Jul 8, 2025 · Updated Nov 4, 2025
Transient execution in affected AMD processors allows local users to infer CPU control-register values despite enabled UMIP. Under specific microarchitectural timing conditions, instructions execute speculatively and expose restricted control-register state through an observable side channel. A low-privilege process must execute on the affected processor; AMD characterizes the result as CPU-configuration disclosure rather than sensitive-data leakage.
Summary
What happened
Transient execution in affected AMD processors allows local users to infer CPU control-register values despite enabled UMIP. Under specific microarchitectural timing conditions, instructions execute speculatively and expose restricted control-register state through an observable side channel. A low-privilege process must execute on the affected processor; AMD characterizes the result as CPU-configuration disclosure rather than sensitive-data leakage.
The record
- CVE
- CVE-2024-36348
- Published
- Jul 8, 2025
- Updated
- Nov 4, 2025
- Vendor
- Advanced Micro Devices, Inc.
- Product
- AMD Ryzen™ 7000 Series Desktop Processors
- Classifications
- CWE-1420, T1005
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Jul 8, 2025CVE publishedPublication date reported by the CVE source.
- Nov 4, 2025Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=all
What conditions does exploitation require?
What is affected?
Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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