Protected-memory access via writable SMPU global-valid bit
Published Dec 5, 2024 · Updated Dec 11, 2024
Memory protection bypass in STMicroelectronics SPC58 devices allows local users with Supervisor code execution to read and write protected memory. The silicon fails to lock the SMPU global-valid bit after region read-only bits are set, so writing zero to GVLD disables bus-master access checks. Supervisor-level code execution is required; the bypass exposes safety-core Flash, EEPROM, and SRAM through peripherals such as DMA or Ethernet.
Summary
What happened
Memory protection bypass in STMicroelectronics SPC58 devices allows local users with Supervisor code execution to read and write protected memory. The silicon fails to lock the SMPU global-valid bit after region read-only bits are set, so writing zero to GVLD disables bus-master access checks. Supervisor-level code execution is required; the bypass exposes safety-core Flash, EEPROM, and SRAM through peripherals such as DMA or Ethernet.
The record
- CVE
- CVE-2023-48010
- Published
- Dec 5, 2024
- Updated
- Dec 11, 2024
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-522, T1687
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Dec 5, 2024CVE publishedPublication date reported by the CVE source.
- Dec 11, 2024Record updatedLatest update available in the CVE record.
Exploitability
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What is affected?
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Published CVSS scores
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Attacks
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Public exploit references
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Technologies
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