Host deadlock via memory-access instruction collision
Published Dec 8, 2023 · Updated Nov 4, 2025
A processor erratum in Arm Cortex-A77 r0p0 and r1p0 allows guest OS users to deadlock a Xen host by triggering a core lockup. The core can deadlock when a device or non-cacheable-memory load executes close to a store-exclusive instruction or a PAR_EL1 register read. Guest-controlled code can trigger the timing-sensitive sequence, deadlocking the core and ultimately the entire system.
Summary
What happened
A processor erratum in Arm Cortex-A77 r0p0 and r1p0 allows guest OS users to deadlock a Xen host by triggering a core lockup. The core can deadlock when a device or non-cacheable-memory load executes close to a store-exclusive instruction or a PAR_EL1 register read. Guest-controlled code can trigger the timing-sensitive sequence, deadlocking the core and ultimately the entire system.
The record
- CVE
- CVE-2023-34320
- Published
- Dec 8, 2023
- Updated
- Nov 4, 2025
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-667, T1499.004
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Dec 8, 2023CVE publishedPublication date reported by the CVE source.
- Nov 4, 2025Record updatedLatest update available in the CVE record.
Exploitability
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What is affected?
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Published CVSS scores
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Attacks
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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