Denial of service via invalid SMU DRAM access
Published Nov 14, 2023 · Updated Aug 2, 2024
Insufficient DRAM address validation in affected AMD processor SMUs allows local users with high privileges to cause denial of service via DMA. The SMU accepts DMA operations targeting invalid DRAM addresses instead of rejecting them, permitting out-of-range reads or writes. Exploitation requires a high-complexity local DMA path; an invalid operation can interrupt the host, with no reported confidentiality impact.
Summary
What happened
Insufficient DRAM address validation in affected AMD processor SMUs allows local users with high privileges to cause denial of service via DMA. The SMU accepts DMA operations targeting invalid DRAM addresses instead of rejecting them, permitting out-of-range reads or writes. Exploitation requires a high-complexity local DMA path; an invalid operation can interrupt the host, with no reported confidentiality impact.
The record
- CVE
- CVE-2023-20533
- Published
- Nov 14, 2023
- Updated
- Aug 2, 2024
- Vendor
- AMD
- Product
- Ryzen 3000 Series Desktop Processors (Matisse)
- Classifications
- T1499
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Nov 14, 2023CVE publishedPublication date reported by the CVE source.
- Aug 2, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=various
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What is affected?
Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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