Simulation failure via misprioritized memory exceptions
Published Jul 18, 2022 · Updated Aug 3, 2024
Improper exception handling in RISC-V ISA Simulator allows local users to cause simulation failure via a crafted guest memory access. In commit ac466a21df442c59962589ba296c702631e041b5, the load path checks alignment and address legality before evaluating a breakpoint trigger, causing a misaligned illegal address to raise the wrong lower-priority trap. Local guest-code execution and a matching watchpoint are required; the resulting trap mismatch can halt conformance or co-simulation workloads.
Summary
What happened
Improper exception handling in RISC-V ISA Simulator allows local users to cause simulation failure via a crafted guest memory access. In commit ac466a21df442c59962589ba296c702631e041b5, the load path checks alignment and address legality before evaluating a breakpoint trigger, causing a misaligned illegal address to raise the wrong lower-priority trap. Local guest-code execution and a matching watchpoint are required; the resulting trap mismatch can halt conformance or co-simulation workloads.
The record
- CVE
- CVE-2022-34643
- Published
- Jul 18, 2022
- Updated
- Aug 3, 2024
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-755, T1499.004
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Jul 18, 2022CVE publishedPublication date reported by the CVE source.
- Aug 3, 2024Record updatedLatest update available in the CVE record.
Exploitability
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What is affected?
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Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
- Upstream exception-priority reproducerproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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