Memory corruption and interruption via arbitrary TMR ranges
Published Aug 13, 2024 · Updated Dec 4, 2024
Improper TMR configuration in affected AMD processors and graphics products allows local users to corrupt memory or interrupt service. The x86 TMR configuration path accepts an attacker-selected address range instead of constraining the protected region to valid boundaries. Exploitation requires high local privileges and difficult platform-specific conditions; successful abuse can alter protected memory and disrupt operation.
Summary
What happened
Improper TMR configuration in affected AMD processors and graphics products allows local users to corrupt memory or interrupt service. The x86 TMR configuration path accepts an attacker-selected address range instead of constraining the protected region to valid boundaries. Exploitation requires high local privileges and difficult platform-specific conditions; successful abuse can alter protected memory and disrupt operation.
The record
- CVE
- CVE-2021-26367
- Published
- Aug 13, 2024
- Updated
- Dec 4, 2024
- Vendor
- Advanced Micro Devices, Inc.
- Product
- AMD Ryzen™ Embedded V1000 Series Processors
- Classifications
- T1499
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Aug 13, 2024CVE publishedPublication date reported by the CVE source.
- Dec 4, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
Affected versions are unavailable in this record. Check the vendor advisory for version and patch details.
What conditions does exploitation require?
What is affected?
Published CVSS scores
CVSS describes severity. EPSS estimates exploitation probability.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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