Service interruption via out-of-range SRAM read
Published May 11, 2022 · Updated Sep 16, 2024
Out-of-bounds read in the SMU mailbox register in 2nd Gen and 3rd Gen AMD EPYC processors allows local users to interrupt service. An insufficient bounds check permits the mailbox register to read beyond the SRAM address range, invoking exception handling. Local low-privileged access to the mailbox path is required, and the documented consequence is service interruption rather than data disclosure.
Summary
What happened
Out-of-bounds read in the SMU mailbox register in 2nd Gen and 3rd Gen AMD EPYC processors allows local users to interrupt service. An insufficient bounds check permits the mailbox register to read beyond the SRAM address range, invoking exception handling. Local low-privileged access to the mailbox path is required, and the documented consequence is service interruption rather than data disclosure.
The record
- CVE
- CVE-2021-26364
- Published
- May 11, 2022
- Updated
- Sep 16, 2024
- Vendor
- AMD
- Product
- AMD EPYC Processors
- Classifications
- CWE-119, T1499
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- May 11, 2022CVE publishedPublication date reported by the CVE source.
- Sep 16, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=various
What conditions does exploitation require?
What is affected?
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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