Data exposure via unfenced reserved DRAM address
Published May 12, 2022 · Updated Sep 17, 2024
Improper DRAM boundary validation in AMD Ryzen and Athlon Series allows local users controlling a UApp or ABL to expose data. The AMD Secure Processor accepts a reserved-DRAM address supplied by the UApp or AGESA Boot Loader without keeping it inside the fenced memory region. Exploitation requires control of one of those firmware components and exposes data outside the processor's intended memory boundary.
Summary
What happened
Improper DRAM boundary validation in AMD Ryzen and Athlon Series allows local users controlling a UApp or ABL to expose data. The AMD Secure Processor accepts a reserved-DRAM address supplied by the UApp or AGESA Boot Loader without keeping it inside the fenced memory region. Exploitation requires control of one of those firmware components and exposes data outside the processor's intended memory boundary.
The record
- CVE
- CVE-2021-26363
- Published
- May 12, 2022
- Updated
- Sep 17, 2024
- Vendor
- AMD
- Product
- AMD Ryzen Series
- Classifications
- Unavailable
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- May 12, 2022CVE publishedPublication date reported by the CVE source.
- Sep 17, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=various
What conditions does exploitation require?
What is affected?
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Weakness, pattern, technique
No sourced classifications are available.
Public exploit references
No public exploit references are available in this record.
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Technologies
Your stack
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Your stack
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