Denial of service via invalid DRAM DMA
Published May 12, 2022 · Updated Sep 16, 2024
Improper input validation in AMD Ryzen Series and Athlon Series SMU firmware allows local users to trigger denial of service via DMA to invalid DRAM addresses. The System Management Unit accepts insufficiently validated DRAM addresses and performs DMA reads or writes to locations outside valid DRAM, which can disrupt SMU operation. Reaching the flaw requires privileged local code able to issue the relevant SMU request; the documented consequence is denial of service, not data disclosure or code execution.
Summary
What happened
Improper input validation in AMD Ryzen Series and Athlon Series SMU firmware allows local users to trigger denial of service via DMA to invalid DRAM addresses. The System Management Unit accepts insufficiently validated DRAM addresses and performs DMA reads or writes to locations outside valid DRAM, which can disrupt SMU operation. Reaching the flaw requires privileged local code able to issue the relevant SMU request; the documented consequence is denial of service, not data disclosure or code execution.
The record
- CVE
- CVE-2021-26351
- Published
- May 12, 2022
- Updated
- Sep 16, 2024
- Vendor
- AMD
- Product
- AMD Ryzen Series
- Classifications
- CWE-20, T1499
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- May 12, 2022CVE publishedPublication date reported by the CVE source.
- Sep 16, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=various
What conditions does exploitation require?
What is affected?
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Public exploit references
No public exploit references are available in this record.
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Technologies
Your stack
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Your stack
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