SMU service interruption via invalid DMA address
Published Nov 16, 2021 · Updated Sep 17, 2024
Insufficient address validation in the SMU on AMD Ryzen and Athlon processors allows local users to interrupt SMU service. The SMU accepts an invalid DRAM address for a DMA read into SRAM and then stops servicing requests from other components. Low-privileged code execution is required, and the published consequence is loss of SMU service rather than code execution or data modification.
Summary
What happened
Insufficient address validation in the SMU on AMD Ryzen and Athlon processors allows local users to interrupt SMU service. The SMU accepts an invalid DRAM address for a DMA read into SRAM and then stops servicing requests from other components. Low-privileged code execution is required, and the published consequence is loss of SMU service rather than code execution or data modification.
The record
- CVE
- CVE-2021-26337
- Published
- Nov 16, 2021
- Updated
- Sep 17, 2024
- Vendor
- AMD
- Product
- AMD Ryzen Series
- Classifications
- T1489
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Nov 16, 2021CVE publishedPublication date reported by the CVE source.
- Sep 17, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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- Affected versionversion=various
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Attacks
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Public exploit references
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