Kernel-address disclosure via PREFETCH timing variation
Published Oct 13, 2021 · Updated Sep 16, 2024
Timing side channel in AMD CPUs allows local users to disclose kernel address-space layout through x86 PREFETCH instructions. PREFETCH execution time varies with the page-table level at which a kernel-address walk aborts, and its timing also exposes TLB state. Unprivileged code can break KASLR locally, but AMD states that the attack does not directly disclose data across address-space boundaries.
Summary
What happened
Timing side channel in AMD CPUs allows local users to disclose kernel address-space layout through x86 PREFETCH instructions. PREFETCH execution time varies with the page-table level at which a kernel-address walk aborts, and its timing also exposes TLB state. Unprivileged code can break KASLR locally, but AMD states that the attack does not directly disclose data across address-space boundaries.
The record
- CVE
- CVE-2021-26318
- Published
- Oct 13, 2021
- Updated
- Sep 16, 2024
- Vendor
- Unknown vendor
- Product
- Unknown product
- Classifications
- CWE-203, CWE-208
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Oct 13, 2021CVE publishedPublication date reported by the CVE source.
- Sep 16, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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What conditions does exploitation require?
What is affected?
Affected products and versions are unavailable in this record.
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Public exploit references
- AMD Prefetch Attacks proof-of-conceptsproof of concept · demonstrated
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Technologies
Your stack
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Your stack
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