Privileged address disclosure via SGX debug messages
Published Feb 17, 2021 · Updated Aug 4, 2024
Information disclosure in Intel 10th Generation Core processors supporting SGX allows local users to read memory-transaction addresses. The disclosed mechanism is a debug message that includes memory-transaction addresses instead of withholding them from diagnostic output. Exploitation requires privileged local access and user interaction, and the documented consequence is limited to confidentiality loss.
Summary
What happened
Information disclosure in Intel 10th Generation Core processors supporting SGX allows local users to read memory-transaction addresses. The disclosed mechanism is a debug message that includes memory-transaction addresses instead of withholding them from diagnostic output. Exploitation requires privileged local access and user interaction, and the documented consequence is limited to confidentiality loss.
The record
- CVE
- CVE-2020-24491
- Published
- Feb 17, 2021
- Updated
- Aug 4, 2024
- Vendor
- Intel Corporation
- Product
- 10th Generation Intel Core Processors
- Classifications
- CWE-20
- Attack vector
- local
- Privileges
- admin
Timeline
How it unfolded
- Feb 17, 2021CVE publishedPublication date reported by the CVE source.
- Aug 4, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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- Affected versionversion=See references
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What is affected?
Published CVSS scores
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Attacks
What attackers are doing with it
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Weakness, pattern, technique
Public exploit references
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Technologies
Your stack
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Your stack
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