SPI ROM protection bypass via privileged-register zeroing
Published Nov 16, 2021 · Updated Sep 17, 2024
Improper input validation in second- and third-generation AMD EPYC PSP firmware allows local users to bypass SPI ROM protections. The PSP accepts a System Management Network operation that zeros any privileged register instead of rejecting the prohibited write. Local low-privileged access is required, and the documented result is removal of SPI ROM protection; no public source demonstrates subsequent firmware modification.
Summary
What happened
Improper input validation in second- and third-generation AMD EPYC PSP firmware allows local users to bypass SPI ROM protections. The PSP accepts a System Management Network operation that zeros any privileged register instead of rejecting the prohibited write. Local low-privileged access is required, and the documented result is removal of SPI ROM protection; no public source demonstrates subsequent firmware modification.
The record
- CVE
- CVE-2020-12961
- Published
- Nov 16, 2021
- Updated
- Sep 17, 2024
- Vendor
- Advanced Micro Devices, Inc.
- Product
- 3rd Gen AMD EPYC Processors
- Classifications
- CWE-20, T1562
- Attack vector
- local
- Privileges
- authenticated
Timeline
How it unfolded
- Nov 16, 2021CVE publishedPublication date reported by the CVE source.
- Sep 17, 2024Record updatedLatest update available in the CVE record.
Exploitability
Present is not the same as exploitable
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Is a vulnerable build present?
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- Affected versionversion=unspecified <MilanPI-SP3_1.0.0.4
What conditions does exploitation require?
What is affected?
Attacks
What attackers are doing with it
Daily unique IPs observed by Shadowserver honeypots for known exploited vulnerabilities (KEVs). Missing observations do not establish an absence of attacks.
Public exploit references
No public exploit references are available in this record.
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Technologies
Your stack
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Your stack
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